1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device using FinFETs.
2. Description of the Related Art
The performance of large-scale integrated circuits formed on a silicon substrate has been getting higher.
This has been realized by scaling the gate length and thinning the gate insulating films on the basis of the scaling rule in metal-insulator-semiconductor (MIS) transistors used in logic circuits or memory devices, such as static random access memory (SRAM) devices.
For example, to improve the cut-off characteristic in a short channel region where the channel length is equal to or shorter than 30 nm, a three-dimensional structure MIS transistor where a projecting region (referred to as a fin) obtained by carving a silicon substrate into thin strip and a gate electrode are crossed in three dimensions has been developed.
The three-dimensional structure MIS transistor, which is known as a Fin field-effect transistor (FinFET), has a double gate structure where a top gate and a back gate are provided on one side face and the other side surface of the fin, respectively.
The FinFET is generally a fully depletion-mode MIS transistor. To suppress a short channel effect, the fin width is made shorter than the gate length in the FinFET.
In recent years, the technique for composing an SRAM using the FinFETs has been proposed (e.g., refer to Jpn. Pat. Appln. KOKAI Publication No. 2005-142289).
An SRAM cell is composed of transfer gate transistors and inverter circuits which are connected so as to form a flip-flop to store data. The MIS transistors constituting the inverter circuit include a load transistor composed of a p-type MIS transistor and a driver transistor composed of an n-type MIS transistor.
Normally, the read stability of the SRAM is determined by the current drive power ratio (I ratio) of the transfer gate transistor to the driver transistor. Therefore, the drive power of the driver transistor is made higher than that of the transfer gate transistor, thereby assuring the stability.
When planar MIS transistors have been used as in the conventional art, adjusting both the gate length and the channel width of them enables the current drive power ratio to be adjusted. However, when SRAM cells are composed of FinFETs, since the channel width of the FinFET is determined by the height of the fin, it is generally difficult to change the height from one FinFET to another in terms of processes. Therefore, it is difficult to adjust the current drive power ration (β ratio) of the driver transistor to the transfer gate transistor by changing the height of the fin.
Accordingly, the β ratio of an SRAM cell composed of conventional FinFETs has been adjusted by changing the number of fins of the driver transistor.